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Espressif Systems /ESP32-H2 /RMT /INT_CLR

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Interpret as INT_CLR

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH1_TX_END)CH1_TX_END 0 (CH3_RX_END)CH3_RX_END 0 (CH0_TX_ERR)CH0_TX_ERR 0 (CH2_RX_ERR)CH2_RX_ERR 0 (CH0_TX_THR_EVENT)CH0_TX_THR_EVENT 0 (CH2_RX_THR_EVENT)CH2_RX_THR_EVENT 0 (CH0_TX_LOOP)CH0_TX_LOOP

Description

Interrupt clear bits

Fields

CH0_TX_END

Set this bit to clear theCH0_TX_END_INT interrupt.
CH1_TX_END

Set this bit to clear theCH1_TX_END_INT interrupt.
CH2_RX_END

Set this bit to clear theCH2_RX_END_INT interrupt.
CH3_RX_END

Set this bit to clear theCH2_RX_END_INT interrupt.
CH1_TX_ERR

Set this bit to clear theCH4_ERR_INT interrupt.
CH0_TX_ERR

Set this bit to clear theCH4_ERR_INT interrupt.
CH3_RX_ERR

Set this bit to clear theCH6_ERR_INT interrupt.
CH2_RX_ERR

Set this bit to clear theCH6_ERR_INT interrupt.
CH1_TX_THR_EVENT

Set this bit to clear theCH1_TX_THR_EVENT_INT interrupt.
CH0_TX_THR_EVENT

Set this bit to clear theCH0_TX_THR_EVENT_INT interrupt.
CH3_RX_THR_EVENT

Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt.
CH2_RX_THR_EVENT

Set this bit to clear theCH2_RX_THR_EVENT_INT interrupt.
CH1_TX_LOOP

Set this bit to clear theCH1_TX_LOOP_INT interrupt.
CH0_TX_LOOP

Set this bit to clear theCH0_TX_LOOP_INT interrupt.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data